(1) Field of the Invention
The present invention relates to semiconductor integrated circuits and especially to a construction using densely integrated cells.
(2) Description of the Related Art
In the field of semiconductor integrated circuit design there exist semi-custom chip design methods known as standard cell methods. According to these methods, chips are designed by combining and arranging logic cells that function as logic circuits.
In the standard cell methods, it is desirable to densely integrate the logic cells and reduce the area of wires connecting to the cells, so as to reduce chip area.
However, when cells of identical width whose input pins have identical width direction locations are arranged in a matrix to form width direction rows and height direction columns, input pin positions of cells in any given column align in an orthogonal direction to the width direction.
Consequently, in the case where input signal wires extend from the height direction, straight signal lines cannot be used within a single wiring layer. Rather, the signal lines must be routed in a roundabout manner, which results in an increase in the amount of wiring required.
This problem is more pronounced in arrays of cells that have a large number of input pins.